1. Technical Field
The present invention relates generally to apparatus and methods for high-performance cooling of multi-chip package structures having multiple chips with disparate cooling requirements mounted on a common substrate. More specifically, the present invention relates to apparatus and methods for packaging multi-chip modules with liquid cooling modules designed to provide different thermal resistances needed for effectively conducting heat from various chips with disparate cooling requirements while minimizing mechanical stresses in thermal bonds due to thermal excursions.
2. Discussion of Related Art
In the design and manufacture of semiconductor IC (integrated circuit) chip packages and modules (e.g., SCM (single chip modules) or MCMs (multi-chip modules)), it is imperative to implement mechanisms that can effectively remove heat generated by IC chip devices (such as microprocessors) to ensure continued reliable operation of the devices. Effective heat removal becomes increasingly problematic as chip geometries are scaled down and operating speeds are increased, which results in increased power density. Although improved IC chip module designs are being developed to operate at higher clock frequencies, increased system performance is increasingly being limited by the ability to implement effective heat removal mechanisms to cool the IC chip modules.
Cooling techniques are especially problematic for a multi-chip module or other multi-chip package structures where an array of chips is mounted on a common substrate. One conventional cooling solution for multiple chips on a common carrier is to thermally couple a thermal hat or package cap/lid/cover to the backside (inactive surface) of the semiconductor IC chips using a mechanically compliant, thermally conductive material (e.g., thermally conductive paste) as a thermal interface. Compliant thermally conductive materials include, for example, thermal pastes, thermal greases, or thermally conductive fluids such as oils, and are frequently referred to as thermal interface materials, or thermal interface materials (TIMs). The package lid or thermal hat, which can be formed of a high thermal conductivity material, such as copper or aluminum, will conduct heat away from the IC chip(s) and the heat is removed from the cooling plate or heat sink by methods such as forced air cooling or circulating liquid coolants.
In general, compliant thermally conductive materials are typically used (as opposed to a rigid or semi-rigid bond) to thermally couple an IC chip to a thermal hat when, for example, the difference in thermal expansion between the material of the IC chip (typically, silicon, Si), the package substrate, which may be a ceramic or polymer, and the material of the thermal hat is relatively large. For large, high performance MCMs, a preferred substrate material is a glass-ceramic, which has a CTE matched to that of silicon. For example, silicon has a linear coefficient of thermal expansion (CTE) of about 2.5 ppm/° C., copper has a CTE of about 16.5 ppm/° C. and aluminum has a CTE of about 23 ppm/° C. Given the significant difference between the thermal expansion between an Si chip, a glass-ceramic substrate, and of a thermal hat made of Cu or Al, and given the large contact area between the thermal hat and the multiple Si chips mounted on a common substrate, there is a relatively long distance for any difference in thermal expansion to act over. In this regard, the use of a compliant thermally conductive material layer as a thermal interface between the chip and thermal hat reduces stress at the thermal interface due to differences in thermal expansion of the IC chip, substrate, and the thermal hat.
Although a rigid bond typically has a lower thermal resistance than a layer of compliant thermally conductive material, the ability to effectively use a rigid bond is limited not only by the difference in the CTEs of the materials that form the thermal hat and the IC chips and substrate, but also on the temperature range (cycle) in which the semiconductor package will operate or be exposed to, as well as size of the area over which the rigid bond will be formed. Indeed, when the thermal expansion of the materials that form the heat spreader, the substrate, and IC chip are closely matched, a rigid bond may be used to thermally couple the heat spreader to the IC chip.
Other techniques include the use of flexible filled polymer adhesive materials to form a “semi-rigid” bond. Such materials can accommodate a limited amount of thermal expansion mismatch between a silicon chip and a copper lid, for example, as long as the area is not too large and the temperature range is not too great. These types of thermal bonds differ from a compliant thermally conductive material layer in that they are not liquid and can tear or delaminate if too great a shear stress is applied. Depending on the polymer used, a filled polymer material can also be a rigid thermal adhesive, such as a silver filled epoxy.
There are various challenges and disadvantages associated with cooling solutions for MCMs using a common thermal hat with a compliant TIM. Differences in thermal expansion between the materials that form the package substrate, the chips, and the thermal hat, for example, can result in both vertical and horizontal deflections during power or temperature cycling. These deflections can lead to the migration of the compliant thermally conductive material out of the gap between the IC chips and the thermal hat, resulting in voids that increase the thermal resistance between the IC chip and the thermal hat and causing local increases in the operating temperature of the IC chips.
Another disadvantage to conventional MCM cooling solutions using a common thermal hat is that the chips mounted to the common substrate may have widely disparate cooling requirements, requiring custom solutions. For example, a processor chip may have a higher power density (W/cm2) than that of a memory chip mounted on the same substrate. When using compliant thermally conductive material as the thermal bond, it is generally desirable to form as thin a layer as possible so as to reduce the thermal resistance for heat conduction from the chips to the thermal hat. However, the chips can vary in thickness and tilt and the substrate may not be perfectly flat, so it is very difficult to establish a thin layer of compliant thermally conductive material between a common cooler and multiple chips.
By way of example, when the chips mounted on a common substrate vary in thickness, the thickness of the bond line will generally be determined by the back surface of the thickest chip. When attaching a thermal hat over multiple chips on a carrier, it is desirable to ensure that the high power chip have the thinnest bond layer of thermally conductive material. If the memory chips were thicker than the processor chip, the thickness of the bond line of the thermally conductive material used to attach the processor chip to the thermal hat would be greater than that of the TIM layer between the thermal hat and the memory chip.
Moreover, maximum allowed device junction temperature may be different for different chips mounted on a common substrate, requiring that the thicknesses of the thermal interface material between some chips and the thermal hat be less than a certain value. The power density of the chips and also the desired junction temperature or power distribution of power on the chip are factors that are considered when determining the thermal resistance required to adequately cool the chips.
Moreover, processor chips and other high-performance chips frequently have a “hot spot” which can have a heat flux (W/cm2) significantly greater than the average heat flux resulting in temperatures 20° C. hotter than the average chip temperature. A thermal solution which may generally be adequate for the average chip power density of various chips mounted on an MCM substrate may not be adequate to allow reliable operation of the hot spot region of the chip.